The present invention relates to a test point circuit, a scan flip-flop for a sequential test, a semiconductor device, and a design device, and relates to, for example, a technique applicable to a logic built-in self test (LBIST).
A general test method of a Large Scale Integration (LSI) includes a scan test. In order to perform the scan test, a flip-flop (FF) in a circuit is substituted with an FF including a multiplexer (MUX) called a scan FF. The MUX is able to switch a test input and a normal operation input by a scan enable signal.
When the scan test is performed, scan FFs are connected in serial and operate as a shift register (this will be referred to as a “scan chain”) that can be controlled and observed from an external terminal of the LSI. The scan chain is subjected to a shift operation so that an arbitrary test pattern (load data) is supplied (loaded) to the respective scan FFs from the test input. This is referred to as a “scan shift operation”. The test pattern set in the respective scan FFs is applied to a combination circuit to be tested.
By switching scan enable signals, an operation result in the combination circuit is captured by the scan FF from the normal operation input. This is called a “capture operation”. The operation result acquired in the capture operation is shifted again by the scan FF and a response is observed (unload). At the same time as this unload, the next test pattern is applied (loaded). By comparing the value unloaded by a tester (unload data) with an expected value, a scan test of the LSI is executed.
In the scan test, it is required that the number of shift cycles correspond to the number of scan FFs connected to the scan chain. Therefore, an extremely large number of test steps are required in the scan test. Further, in order to execute the scan test of the LSI, it is required to store test data including the expected value of the load data and the unload data required for the scan shift operation in a memory of the tester. When the number of test steps is too large, the test data cannot be contained in the memory of the tester, and thus the necessary test cannot be performed.
As one example of a design for testability (DFT) that reduces the amount of test data, a logic built-in self test (LBIST) has been proposed (Debaleena Das, Nur A. Touba, “Reducing test data volume using external/LBIST hybrid test patterns”, International Test Conference 2000). In the LBIST, the load data generated from a pseudo random pattern generator (PRPG) inside the circuit is supplied to the scan chain and the scan shift operation is performed, and the unload data after the capture operation is compressed by a response compressor (Multiple Input Signature Register: MISR) inside the circuit.
Therefore, while the scan test by the LBIST is being performed there is no need to apply the test data from an external tester and the test can be executed by only supplying clocks. After the test is performed for a desired period of time, the value compressed by the MISR is observed by the external tester, whereby it is determined whether there is a failure. Therefore, the only test data required for the external tester is a control sequence of the LBIST controller, initial values of the PRPG and the MISR, and an expected value of the value output from the MISR.